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IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
JULY 2010
FEATURES
HIGH SPEED: (IS61/64WV25616ALL/BLL) * High-speed access time: 8, 10, 20 ns * Low Active Power: 85 mW (typical) * Low Standby Power: 7 mW (typical) CMOS standby LOW POWER: (IS61/64WV25616ALS/BLS) * High-speed access time: 25, 35, 45 ns * Low Active Power: 35 mW (typical) * Low Standby Power: 0.6 mW (typical) CMOS standby * Single power supply -- VDD 1.65V to 2.2V (IS61WV25616Axx) * * * * * -- VDD 2.4V to 3.6V (IS61/64WV25616Bxx) Fully static operation: no clock or refresh required Three state outputs Data control for upper and lower bytes Industrial and Automotive temperature support Lead-free available
DESCRIPTION The ISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx
are high-speed, 4,194,304-bit static RAMs organized as 262,144 words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV25616Axx/Bxx and IS64WV25616Bxx are packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16 MEMORY ARRAY
VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE OE WE UB LB CONTROL CIRCUIT
Copyright (c) 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. G 07/15/2010
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
TRUTH TABLE
Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN VDD Current ISB1, ISB2 ICC ICC
Write
ICC
PIN CONFIGURATIONS 44-Pin TSOP (Type II) and SOJ
PIN DESCRIPTIONS
A0-A17 I/O0-I/O15 CE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10
OE WE LB UB NC VDD GND
*SOJ package under evaluation.
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Rev. G 07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
PIN CONFIGURATIONS 44-Pin LQFP
48-Pin mini BGA (6mm x 8mm)
1 2 3 4 5 6
1 2
CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7
44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22
WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A17 A16 A15 A14 A13 A12 A11 A10 OE UB LB
I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC
A B C D E F G H
LB I/O8 I/O9 GND VDD I/O14 I/O15 NC
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
A0 A3 A5 A17 NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
N/C I/O0 I/O2 VDD GND I/O6 I/O7 NC
3 4 5 6 7 8 9 10 11 12
*LQFP package under evaluation.
PIN DESCRIPTIONS
A0-A17 I/O0-I/O15 CE OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5%
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VDD GND VOUT VDD, Outputs Disabled Test Conditions VDD = Min., IOH = -4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 -- 2 -0.3 -1 -1 Max. -- 0.4 VDD + 0.3 0.8 1 1 Unit V V V V A A
Note: 1. VIL (min.) = -0.3V DC; VIL (min.) = -2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VDD GND VOUT VDD, Outputs Disabled Test Conditions VDD = Min., IOH = -1.0 mA VDD = Min., IOL = 1.0 mA Min. 1.8 -- 2.0 -0.3 -1 -1 Max. -- 0.4 VDD + 0.3 0.8 1 1 Unit V V V V A A
Note: 1. VIL (min.) = -0.3V DC; VIL (min.) = -2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V
Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND VIN VDD GND VOUT VDD, Outputs Disabled Test Conditions IOH = -0.1 mA IOL = 0.1 mA VDD 1.65-2.2V 1.65-2.2V 1.65-2.2V 1.65-2.2V Min. 1.4 -- 1.4 -0.2 -1 -1 Max. -- 0.2 VDD + 0.2 0.4 1 1 Unit V V V V A A
Note: 1. VIL (min.) = -0.3V DC; VIL (min.) = -2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0V to 3V 1V/ ns 1.5V See Figures 1 and 2 Unit (3.3V + 10%) 0V to 3V 1V/ ns 1.5V See Figures 1 and 2 Unit (1.65V-2.2V) 0V to 1.8V 1V/ ns 0.9V See Figures 1 and 2
1 2 3 4
353
AC TEST LOADS
319 3.3V
ZO = 50 OUTPUT
50 1.5V
OUTPUT
30 pF Including jig and scope
5 6 7 8 9 10 11 12
5 pF Including jig and scope
Figure 1.
Figure 2.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value -0.5 to VDD + 0.5 -0.3 to 4.0 -65 to +150 1.0 Unit V V C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
HIGH SPEED (IS61WV25616ALL/BLL)
OPERATING RANGE (VDD) (IS61WV25616ALL)
Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Automotive -40C to +125C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 20ns 20ns 20ns
1 2 3 4 5 6 7
-10 Min. Max. -- -- -- 25 -- -- -- -- -- -- -- -- -- 2 40 45 65 35 40 60 10 15 30 8 9 20 -20 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- 35 40 60 30 40 60 10 15 30 8 9 20 Unit mA
OPERATING RANGE (VDD) (IS61WV25616BLL)(1)
Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C VDD (8 nS)1 3.3V + 5% 3.3V + 5% VDD (10 nS)1 2.4V-3.6V 2.4V-3.6V
Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns.
OPERATING RANGE (VDD) (IS64WV25616BLL)
Range Automotive Ambient Temperature -40C to +125C VDD (10 nS) 2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 Symbol Parameter ICC VDD Dynamic Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Com. Ind. Auto. typ.(2) Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. typ.(2) Min. -- -- -- -- -- -- -- -- -- -- -- -- Max. 50 55 -- 35 40 -- 10 15 -- 8 9 --
8 9 10 11 12
ICC1
Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs)
VDD = Max., IOUT = 0 mA, f = 0 VDD = Max., VIN = VIH or VIL CE VIH, f = 0 VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0
mA
ISB1
mA
ISB2
mA
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
LOW POWER (IS61WV25616ALS/BLS)
OPERATING RANGE (VDD) (IS61WV25616ALS)
Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Automotive -40C to +125C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 45ns 45ns 45ns
OPERATING RANGE (VDD) (IS61WV25616BLS)
Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C VDD (25 nS) 2.4V-3.6V 2.4V-3.6V
OPERATING RANGE (VDD) (IS64WV25616BLS)
Range Automotive Ambient Temperature -40C to +125C VDD (35 nS) 2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC VDD Dynamic Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Com. Ind. Auto. typ.(2) Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. typ.(2) -25 Min. Max. -- -- -- 11 -- -- -- -- -- -- -- -- -- 0.2 10 12 20 5 7 10 1 2 10 -- -- -- -- -- -- -- -- -- 10 12 20 5 7 10 1 2 10 -- -- -- -- -- -- -- -- -- 10 12 20 5 7 10 1 2 10 mA 20 25 50 -35 Min. Max. -- -- -- 20 25 50 -45 Min. Max. -- -- -- 15 20 40 Unit mA
ICC1
Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs)
VDD = Max., IOUT = 0 mA, f = 0 VDD = Max., VIN = VIH or VIL CE VIH, f = 0 VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0
ISB1
mA
ISB2
mA
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Power Up Time Power Down Time Min. 8 -- 2.0 -- -- -- 0 0 3 -- 0 0 0 -- Max. -- 8 -- 8 4.5 3 -- 3 -- 5.5 3 -- -- 8 -10 Min. Max. 10 -- 2.0 -- -- -- 0 0 3 -- 0 0 0 -- -- 10 -- 10 4.5 4 -- 4 -- 6.5 3 -- -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 2 3 4 5 6 7 8 9 10 11 12
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output -20 ns Min. Max. 20 -- 2.5 -- -- 0 0 0 3 -- 0 0 -- 20 -- 20 8 8 -- 8 -- 8 8 -- -25 ns Min. Max. 25 -- 4 -- -- 0 0 0 10 -- 0 0 -- 25 -- 25 12 8 -- 8 -- 25 8 -- -35 ns Min. Max. 35 -- 4 -- -- 0 0 0 10 -- 0 0 -- 35 -- 35 15 10 -- 10 -- 35 10 -- -45ns Min. Max. 45 -- 7 -- -- 0 0 0 15 -- 0 0 -- 45 -- 45 20 15 -- 15 -- 45 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE tLZCE tBA tHZB tLZB
(2 (2)
Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
1 2
t OHA
DATA VALID
READ1.eps
t RC
ADDRESS
t AA t OHA
DOUT
PREVIOUS DATA VALID
3 4
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
5 6
tAA tOHA tDOE tHZOE
OE
7 8
CE
tLZOE tACE tLZCE tHZCE
LB, UB
DOUT
HIGH-Z
tLZB
tBA
tRC
DATA VALID
tHZB
VDD
Supply Current
tPU
50%
tPD
ICC
50%
9 10 11 12
ISB
UB_CEDR2.eps
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
(2)
-10 Max. -- -- -- -- -- -- -- -- -- -- 3.5 -- Min. 10 8 8 0 0 8 8 10 6 0 -- 2 Max. -- -- -- -- -- -- -- -- -- -- 5 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
Min. 8 6.5 6.5 0 0 6.5 6.5 8.0 5 0 -- 2
tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(2) tLZWE
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
(3)
-20 ns Min. Max. 20 12 12 0 0 12 12 17 9 0 -- 3 -- -- -- -- -- -- -- -- -- -- 9 --
-25 ns Min. Max. 25 18 15 0 0 18 18 20 12 0 -- 5 -- -- -- -- -- -- -- -- -- -- 12 --
-35 ns Min. Max. 35 25 25 0 0 30 30 30 15 0 -- 5 -- -- -- -- -- -- -- -- -- -- 20 --
-45ns Min. Max. 45 35 35 0 0 35 35 35 20 0 -- 5 -- -- -- -- -- -- -- -- -- -- 20 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
1 2 3 4 5 6 7 8 9 10 11 12
tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(3) tLZWE
Notes: 1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )
t WC
ADDRESS
VALID ADDRESS
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CEWR1.eps
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE).
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW t PWE1
WE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CEWR2.eps
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
1 2
t HA
OE CE
LOW
LOW
t AW t PWE2
WE
3
t LZWE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
4 5
UB_CEWR3.eps
t SD
DIN
t HD
DATAIN VALID
6
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
ADDRESS 1
7 8
t HA
t WC
ADDRESS 2
OE
t SA
CE
LOW
WE
t HA t SA t PBW t PBW
WORD 2
9 10
UB_CEWR4.eps
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
11 12
Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
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IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
HIGH SPEED (IS61WV25616ALL/BLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter VDD for Data Retention Data Retention Current Test Condition See Data Retention Waveform VDD = 2.0V, CE VDD - 0.2V Com. Ind. Auto. Options Min. 2.0 -- -- 0 Typ.(1) -- 2 -- -- -- Max. 3.6 8 9 15 -- -- Unit V mA
VDR
IDR
tSDR tRDR
Data Retention Setup Time Recovery Time
See Data Retention Waveform See Data Retention Waveform
O
ns ns
tRC
Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested.
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.2V, CE VDD - 0.2V See Data Retention Waveform See Data Retention Waveform
O
Options Com. Ind.
Min. 1.2 -- -- 0
Typ.(1) -- 5 -- -- --
Max. 3.6 10 15 -- --
Unit V mA ns ns
VDR
IDR
tSDR tRDR
tRC
Note 1: Typical values are measured at VDD = 1.8V, TA = 25 C and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR VDD
Data Retention Mode
tRDR
VDR CE VDD - 0.2V
CE GND
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. G 07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
LOW POWER (IS61WV25616ALS/BLS)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter VDD for Data Retention Data Retention Current Test Condition See Data Retention Waveform VDD = 2.0V, CE VDD - 0.2V Com. Ind. Auto. Options Min. 2.0 -- -- 0 Typ.(1) -- 0.2 -- -- -- Max. 3.6 1 2 10 -- -- Unit V mA
1 2 3 4
Min. 1.2 -- -- 0 Typ.(1) -- 0.2 -- -- -- Max. 3.6 1 2 -- -- Unit V mA ns ns
VDR
IDR
tSDR tRDR
Data Retention Setup Time Recovery Time
See Data Retention Waveform See Data Retention Waveform
O
ns ns
tRC
Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested.
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.2V, CE VDD - 0.2V See Data Retention Waveform See Data Retention Waveform
O
Options Com. Ind.
VDR
IDR
5 6 7
tSDR tRDR
tRC
: Typical values are measured at VDD = 1.8V, TA = 25 C and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
8
tRDR
tSDR VDD
Data Retention Mode
9 10
VDR CE VDD - 0.2V
CE GND
11 12
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. G 07/15/2010
17
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
ORDERING INFORMATION (HIGH SPEED) Commercial Range: 0C to +70C Voltage Range: 2.4V to 3.6V
Speed (ns) 10 (81) Order Part No. IS61WV25616BLL-10TL Package TSOP (Type II), Lead-free
Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V.
Industrial Range: -40C to +85C Voltage Range: 2.4V to 3.6V
Speed (ns) 10 (8 )
1
Order Part No. IS61WV25616BLL-10BI IS61WV25616BLL-10BLI IS61WV25616BLL-10TI IS61WV25616BLL-10TLI
Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free
Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V.
Industrial Range: -40C to +85C Voltage Range: 1.65V to 2.2V
Speed (ns) 20 Order Part No. IS61WV25616ALL-20BI IS61WV25616ALL-20TI IS61WV25616ALL-20TLI Package 48 mini BGA (6mm x 8mm) TSOP (Type II) TSOP (Type II), Lead-free
Automotive Range: -40C to +125C Voltage Range: 2.4V to 3.6V
Speed (ns) 10 Order Part No. IS64WV25616BLL-10BA3 IS64WV25616BLL-10BLA3 IS64WV25616BLL-10CTA3 IS64WV25616BLL-10CTLA3 Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe
18
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. G 07/15/2010
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
ORDERING INFORMATION (LOW POWER) Industrial Range: -40C to +85C Voltage Range: 2.4V to 3.6V
Speed (ns) 25 Order Part No. IS61WV25616BLS-25TLI Package TSOP (Type II), Lead-free
1 2 3
Package TSOP (Type II), Lead-free
Industrial Range: -40C to +85C Voltage Range: 1.65V to 2.2V
Speed (ns) 45 Order Part No. IS61WV25616ALS-45TLI
4 5 6 7 8 9 10 11 12
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. G 07/15/2010
19
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
NOTE :
1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207
20
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. G 07/15/2010
Package Outline
08/12/2008
Rev. G 07/15/2010
Integrated Silicon Solution, Inc. -- www.issi.com
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS
NOTE :
1. CONTROLLING DIMENSION : MM 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
Package Outline
06/04/2008
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